1. Field of the Invention
The present invention relates to active-matrix display devices which include pixels (pixel circuits) having display elements arranged in a matrix and which write and display image data with scanning lines and signal lines and to methods of driving such active-matrix display devices. In particular, the present invention relates to an active-matrix display device having, for example, an organic electroluminescent (referred to as EL hereinafter) element as a display element, and to a method of driving the active-matrix organic-EL display device.
2. Description of the Related Art
In active-matrix display devices, an electro-optical element, such as a liquid crystal cell or an organic-EL element, is used for the display element of each pixel. The organic-EL element has a structure in which an organic layer is disposed between electrodes. By applying a voltage to the organic-EL element, electrons are injected into the organic layer from the cathode and holes are injected into the organic layer from the anode. The electrons and the holes then recombine to emit light. Organic-EL elements have the following characteristics:
1. Organic-EL elements require low-power consumption, less than or equal to 10 V, for driving to achieve a luminance of 100 to 10,000 cd/m2.
2. Organic-EL elements have a high image contrast due to being self-luminous, have good visibility due to their high response speed, and are also suitable for moving image displays; and
3. Organic-EL elements are all-solid-state elements having a simple structure, thus achieving high reliability and low-profile elements.
Organic-EL display devices (referred to as organic-EL displays hereinafter) having organic-EL elements with such characteristics for the display elements of the pixels are expected to be used as next-generation flat panel displays.
As methods for driving organic-EL displays, a simple-matrix method and an active-matrix method are known. Of these two methods, the active-matrix method has the following characteristics:
1. The active-matrix method is capable of maintaining the light emission of the organic-EL element of each pixel within a period of one frame and is thus suitable for high-definition and high-luminance organic-EL displays; and
2. The active-matrix method is capable of having a peripheral circuit with thin film transistors formed on a panel so as to simplify the external interface of the panel and also to achieve a highly-functional panel.
In active-matrix organic-EL displays, polysilicon thin film transistors (referred to as TFTs hereinafter) having polysilicon as the active layer are commonly used for the transistors, that is, active elements. The reasons for this common use of polysilicon TFTs are their superior driving ability and their capability of reducing the pixel size to achieve high definition. On the other hand, however, polysilicon TFTs are also known for having highly irregular characteristics.
Accordingly, for an active-matrix organic-EL display using the polysilicon TFTs, irregularities in the characteristics of the TFTs need to be reduced and the irregularities of the TFTs in the circuits need to be compensated. This is due to the following reason. In a liquid crystal display having liquid crystal cells as the display elements of the pixels, the luminance data of the pixels is controlled by a voltage, whereas in an organic-EL display, the luminance data of the pixels is controlled by an electrical current.
A general outline of the active-matrix organic-EL display will now be described. Referring to FIG. 11, a schematic view of the active-matrix organic-EL display is illustrated. Referring to FIG. 12, a diagram of one of the pixel circuits of the active-matrix organic-EL display is illustrated (for an example, see Japanese Unexamined Patent Application Publication No. 8-234683). In the active-matrix organic-EL display, m columns×n rows of pixels 101 are arrayed in a matrix. In the matrix-arrayed pixels 101, each of m columns of signal lines 103-1 to 103-m, which are driven by a data driver 102, is connected with the pixels 101 in a corresponding pixel column, and each of n rows of scanning lines 105-1 to 105-n, which are driven by a scan driver 104, is connected with the pixels 101 in a corresponding pixel row.
As is apparent from FIG. 12, each of the pixels (pixel circuits) 101 includes an organic-EL element 110, a first transistor 111, a second transistor 112, and a capacitor 113. A N-channel transistor is used for the first transistor 111, and a P-channel transistor is used for the second transistor 112.
A source terminal of the first transistor 111 is connected with a corresponding one of the signal lines 103 (103-1 to 103-m), and a gate terminal is connected with a corresponding one of the scanning lines 105 (105-1 to 105-n). A first end of the capacitor 113 is connected with a first power line 121 of a power-supply voltage VCC1, which may be, for example, a positive supply voltage. A second end of the capacitor 113 is connected with a drain terminal of the first transistor 111. A source terminal of the second transistor 112 is connected with the first power line 121, and a gate terminal of the second transistor 112 is connected with the drain terminal of the first transistor 111. An anode of the organic-EL element 110 is connected with a drain terminal of the second transistor 112, and a cathode of the organic-EL element 110 is connected with a second power line 122 of a power-supply voltage VCC2, which may be, for example, a ground potential.
In the pixel circuit described above, a row which includes one of the pixels that writes the luminance data is selected by the scan driver 104 via the scanning line 105. This turns ON the first transistors 111 of the pixels in the row. The luminance data is supplied through a voltage from the data driver 102 via the signal line 103. The luminance data is then transmitted through the first transistor 111 and is written into the capacitor 113, which holds the data voltage. The luminance data written in the capacitor 113 is held for a period of one field. The held data voltage is applied to the gate terminal of the second transistor 112.
The second transistor 112 drives the organic-EL element 110 with electrical current according to the held data. A grayscale is achieved in the organic-EL element 110 by modulating the voltage Vdata (<0) held by the capacitor 113 between the gate and the source of the second transistor 112.
The luminance Loled of the organic-EL element is usually proportional to the electrical current Ioled in the element. Consequently, the following equation holds between the luminance Loled and the electrical current Ioled of the organic-EL element:Loled∝Ioled=k(Vdata−Vth)2  (1)
In Equation (1), k=1/2·μ·Cox·W/L, where μ indicates the carrier mobility of the second transistor, Cox indicates the gate capacitance per unit area of the second transistor 112, W indicates the gate width of the second transistor 112, and L indicates the gate length of the second transistor 112. Accordingly, the mobility μ of the second transistor 112 and irregularities in the threshold voltage Vth (<0) directly affect the luminance irregularities of the organic-EL element.
To compensate for the threshold voltage Vth, which tends to cause luminance irregularities easily, a threshold voltage compensation pixel circuit is presented in, for example, U.S. Pat. No. 6,229,506.
FIG. 13 is a circuit diagram of a conventional threshold voltage compensation pixel circuit. In FIG. 13, similar parts as in FIG. 12 are indicated with the same reference numerals. As is apparent from FIG. 13, this conventional pixel circuit includes an organic-EL element 110, four transistors 111, 112, 114, and 115, and two capacitors 113 and 116. In an organic-EL display having this pixel circuit, three scanning lines 105A, 105B, and 105C, which are driven by a scan driver 104 (see FIG. 11), are interconnected with corresponding rows of pixels.
A source terminal of the first transistor 111 is connected with a signal line 103, and a gate terminal of the first transistor 111 is connected with a first scanning line 105A. A first end of the first capacitor 116 is connected with the drain terminal of the first transistor 111. A gate terminal of the second transistor 112 is connected with a second end of the first capacitor 116, and a source terminal of the second transistor 112 is connected with a first power line 121 of a power-supply voltage VCC1, which may be, for example, a positive supply voltage. A first end of the second capacitor 113 is connected with the first power line 121, and a second end of the second capacitor 113 is connected with the gate terminal of the second transistor 112.
A gate terminal of a third transistor 114 is connected with a second scanning line 105B, a source terminal of the third transistor 114 is connected with the gate terminal of the second transistor 112, and a drain terminal of the third transistor 114 is connected with the drain terminal of the second transistor 112. A gate terminal of a fourth transistor 115 is connected with a third scanning line 105C, and a source terminal of the fourth transistor 115 is connected with the drain terminal of the second transistor 112. An anode of the organic-EL element 110 is connected with a drain terminal of the fourth transistor 115, and the cathode is connected with the second power line 122 of a power-supply voltage VCC2, which may be, for example, a ground potential.
The operation of the conventional threshold voltage compensation pixel circuit will now be described with reference to the timing diagram of FIG. 14. This timing diagram describes the timing relationship of an i-th row and an (i+1)-th row in the pixel circuit during driving. Furthermore, the term “compensate” refers to the threshold voltage compensation period, the term “write” refers to the data writing period, and the term “hold” refers to the data holding period.
In the operation of this pixel circuit, the threshold voltage compensation period comes before the data writing period. In this threshold voltage compensation period, a scanning pulse SCAN1 is supplied via the first scanning line 105A at a high level (referred to as an “H” level hereinafter) to turn the first transistor 111 ON. A fixed voltage Vo is then supplied to the signal line 103 from the data driver 102. Thus, the fixed voltage Vo is written into the first capacitor 116 via the first transistor 111. A scanning pulse SCAN2 supplied via the second scanning line 105B also reaches the “H” level at this time to turn ON the third transistor 114. Also, since a scanning pulse SCAN3 supplied via the third scanning line 105C is at a low level (referred to as an “L” level hereinafter), the fourth transistor 115 is OFF.
In this state, the first capacitor 116 having the fixed voltage Vo adjacent to the first end of the capacitor 116 is charged from the second end via the source and drain terminals of the third transistor 114. If the threshold voltage compensation period is long enough, the voltage adjacent to the second end of the first capacitor 116, that is, the voltage between the gate and the source terminals of the second transistor 112, converges toward the threshold voltage Vth (<0) of the transistors.
In the subsequent data writing period, since the scanning pulse SCAN1 is maintained at the “H” level, the first transistor 111 is kept in an ON mode, and data voltage Vo+Vdata (Vdata<0) is supplied from the signal line 102. Because the scanning pulse SCAN2 is at the “L” level at this time, the third transistor 114 is OFF.
By neglecting, for example, the gate capacitance or the parasitic capacitance of the transistors, the voltage between the gate and source terminals of the second transistor 112 can be represented by the following equation:Vgs=Vth+C1/(C1+C2)·Vdata  (2)where C1 and C2 indicate the capacitance of the first and second capacitors 116 and 113, respectively.
By applying equation (2), the electrical current Ioled flowing through the organic-EL element 110 can be represented by the following equation:Ioled∝Ioled=k{C1/(C1+C2)·Vdata}2  (3)
As is apparent from equation (3), the electrical current Ioled flowing through the organic-EL element 110 is not affected by the threshold voltage Vth of the second transistor 112. In other words, by using the conventional threshold voltage compensation pixel circuit, the threshold voltage Vth of the transistor 112 of each pixel is compensated. This means that irregularities in the threshold voltage Vth of the second transistor 112 do not cause the luminance irregularities of the organic-EL element 110.
In the conventional threshold voltage compensation pixel circuit described above, during the threshold voltage compensation period, the second transistor 112 is gradually turned OFF as the voltage between the source terminal and the gate terminal approaches the threshold voltage Vth. This also deactivates its operation and requires too much time for the voltage between the source terminal and the gate terminal of the transistor 112 to converge toward the threshold voltage Vth. For this reason, the threshold voltage compensation period requires a large amount of time.
The differential equation of the gate voltage of the second transistor 112 in the threshold voltage compensation period is as follows:k·{Vgs(t)−Vth}2=−Cs·dVgs/dt  (4)
In equation (4), a sufficient length of the threshold voltage compensation period is considered to be the time required for the amount of electrical current to be half of the amount during the minimum luminance.
If the electrical current value during the maximum luminance of the organic-EL element 110 is represented by Imax, the initial value of the voltage Vgs between the gate terminal and the source terminal of the second transistor 112 is indicated by Vinit, the hold capacitor of the gate voltage of the second transistor 112, which is mainly the capacitance C1 of the second capacitor 113, is indicated by Cs, the grayscale value is indicated by n, and the voltage Vgs between the gate terminal and the source terminal that provides the electrical current Imax during the maximum luminance is represented by Vgs=ΔV+Vth, then the following equation describes the time required for the amount of electrical current to be half of the amount during the minimum luminance, which is indicated by Imax/2 (n−1)t=Cs·ΔV/Imax{√(2n−2)−ΔV/Vinit}  (5)
For example, if Cs=1 [pF], n=64, ΔV=4, and Imax=1 [μA] and if the second term is sufficiently small, then t=45 [μs]. On the other hand, if the resolution (graphics display standard) is VGA, the number of the scanning lines is 480, and the frame frequency is 60 Hz, then one horizontal period is about 30 μs. This means that it is difficult to complete the threshold voltage compensation period in one horizontal period.
Accordingly, in a VGA-class display, a sufficient length of the threshold voltage compensation period requires several μs to several tens of μs. For this reason, it is difficult to perform the threshold voltage compensation and the data writing continuously within one horizontal period. In other words, the conventional threshold voltage compensation pixel circuit cannot be applied to a VGA-class organic-EL display. Furthermore, as the display becomes more highly defined, one horizontal period, which is inversely proportional to the number of scanning lines, becomes shorter. Thus, a sufficient length of the threshold voltage compensation period is even more difficult to maintain.
In the conventional threshold voltage compensation pixel circuit, a signal-line voltage corresponding to the threshold voltage compensation period and the data writing period, that is, the fixed voltage Vo during the threshold voltage compensation period and the data voltage Vdata+fixed voltage Vo during the data writing period, must be supplied from the signal line 103. For this reason, the structure of the data driver 102 (see FIG. 11), which is the signal line driving circuit, tends to be complex.